RJC688 | Sr Digital CAD Engineer – RTL to GDS II flow

This opening is with global leading product development company. Looking to hire senior digital CAD engineer and digital CAD engineer Experience in physical design.

Department: Product Development
Project Location(s): Bangalore
Education: Engineering
Compensation: More Than Industry Standards
  1. Sr or Lead Digital CAD Engineer with 6 to 12 years of experience.
    1. Physical design or implementation
    2. RTL to GDS and tapeout experiences
    3. Floorplan and Place & route expertise
    4. Low-power implementation experience is an added advantage
  2. As part of dynamic team focused on Digital Implementation with emphasis on low power design experience, Power, Rail and Static Timing Analysis of Digital/Mixed Signal SoCs and the supporting CAD/EDA tools/methodologies.
  3. Even though the candidate will be part of the CAD/methodology team, he/she will be working very closely with the implementation teams from different business units.
  4. Candidate should possess strong physical design or digital implementation experience including experience in taping out multiple products at full chip level.
  5. Develop and drive methodologies that enable Implementation and signoff flows for the entire company emphasizing on low power design implementation for digital/mixed-signal SoCs
  6. Work with global methodology development team to automate and integrate the above flows for centralized deployment
  7. Evaluate and deploy the integrations between the implementation and signoff tools
  8. Provide strong technical leadership and support to various Business Units and ensure successful tapeouts of their products.
  9. Expertise in overall digital implementation (RTL to GDS II flow) and has a well-proven track record of being involved in successful multi-million gate SOC design tapeouts in nanometer technology.
  10. Strong experience in low power design and implementation methodologies having supported successful tapeouts using IEEE 1801
  11. Strong experience in developing and supporting power intent definitions (UPF/CPF) for low-power designs, low power based synthesis, low power static checking .
  12. Strong experience in low power based floorplanning activities including power and IR analysis and physical implementation.
  13. Experience in working on advanced nanometer and finfet technologies.
  14. Strong experience in automation of methodologies/solution using TCL, Python, PERL and Tk.
  15. Should possess excellent interpersonal and communication skills to collaborate and influence design development groups across the globe